The present invention relates to a method of manufacturing a semiconductor device and the semiconductor device and particularly to a semiconductor device in which a high withstand voltage MOS transistor and a low withstand voltage MOS transistor are integrated in one identical semiconductor chip, and trench isolation is adopted.
In recent semiconductor devices, a configuration in which a high withstand voltage MOS transistor and a low withstand voltage MOS transistor are disposed in respective regions is sometimes adopted, for example, as in liquid crystal display (LCD) drivers. This configuration enables integration of circuits operating at different power source voltages in one identical semiconductor chip.
A high withstand voltage MOS transistors and a low withstand voltage MOS transistors have to be controlled independently by eliminating electric interference between the devices. In a method of electrically isolating the devices, shallow trench isolation (STI) of forming a trench in a substrate and burying an insulation material therein has been widely used as means for attaining refinement. The trench isolation is disclosed, for example, in Japanese Unexamined Patent Publication No. Hei 11 (1999)-150180.
When the trench isolation is utilized in the device isolation not only for low withstand voltage MOS transistors but also for high withstand voltage MOS transistors, this provides an advantage capable of device isolation at a small isolation width between devices while maintaining high withstanding voltage. Accordingly, a configuration of using the trench isolation in device isolation both for the high withstand voltage MOS transistor and the low withstand voltage MOS transistor has been progressed rapidly in the application to products of using the high withstand voltage CMOS process such as in LCD drivers. For example, Japanese Unexamined Patent Publication No. 2006-253499 discloses a configuration of using trench isolation in device isolation both for the high withstand voltage MOS transistor and low withstand voltage MOS transistor.
FIG. 1A to FIG. 1C, FIG. 2A to FIG. 2C, and FIG. 3A to FIG. 3C show an example of a method of manufacturing a semiconductor device using trench isolation in device isolation both for a high withstand voltage MOS transistor and a low withstand voltage MOS transistor. In each of FIG. 1A to FIG. 1C, FIG. 2A to FIG. 2C, and FIG. 3A to FIG. 3C, the left part of the drawing shows a structure of a high withstand voltage region where a high withstand voltage MOS transistor is formed and the right part of the drawing shows a structure of a low withstand voltage region where a low withstand voltage MOS transistor is formed. A similar manufacturing method is disclosed also in Japanese Unexamined Patent Publication No. 2006-253499.
In the manufacturing method, as shown in FIG. 1A, a thermal oxide film 102 and a silicon nitride film 103 are formed at first over the surface of a silicon substrate 101. Successively, a resist film 104 is formed by photolithography. By using the resist film 104 as a mask, the thermal oxide film 102 and the silicon nitride film 103 are patterned, and successively, the silicon substrate 101 is shallowly dry etched to form a shallow trench 105. The side wall of the shallow trench 105 forms a portion of a trench formed by a process to be described later and is hereinafter referred to as a tapered portion 105a. The tapered portion 105a is formed so as to have a desired taper angle (angle to the surface of the silicon substrate 101). The taper angle of the tapered portion 105a is preferably 45 degree.
Successively, as shown in FIG. 1B, a deposition film 106 is formed over the entire surface including the side wall of the resist film 104, the side wall of the silicon nitride film 103, and the side wall of the thermal oxide film 102. The deposition film 106 is deposited by generating plasmas in a gas mixture comprising a fluorocarbon gas (for example, C4F8) not containing hydrogen and a CO gas. Further, as shown in FIG. 1C, the silicon substrate 101 is anisotropically etched to form a trench 107. In this case, the deposition film 106 serves as a side wall to protect the tapered portion 105a having a desired taper angle. The taper angle of the main portion 107a of the trench 107 is made steeper than that of the tapered portion 105a (that is, angle formed to the surface of the silicon substrate 101 is larger).
Then, when the resist film 104 and the deposition film 106 are removed, a trench 107 having a shape where the tapered portion 105a at a taper angle of 45 degrees is formed only to the opening edge is obtained. Successively, as shown in FIG. 2A, rounding-off oxidation is performed in the next step to form a thermal oxide film 108. Further, after burying a buried oxide film 109 in the trench 107, polishing is performed using the silicon nitride film 103 as a stopper. Thus, a portion of the buried oxide film 109 is removed and additional etching is performed so that the remaining buried oxide film 109 has a desired height.
Further, as shown in FIG. 2B, a desired trench isolation structure is formed by selectively removing the silicon nitride film 103 and the thermal oxide film 102 therebelow. In this step, an indent referred to as a divot is formed in the buried oxide film 109 used for trench isolation when the thermal oxide film 102 below the silicon nitride film 103 is removed. The divot is shown by reference 110 in FIG. 2B. Formation of the divot is also disclosed, for example, in Japanese Unexamined Patent Publication No. 2003-133549.
Then, as shown in FIG. 2C, a thick gate oxide film 111 is formed by thermal oxidation for forming a high withstand voltage MOS transistor. The thick gate oxide film 111 is formed in both of the high withstand voltage region and the low withstand voltage region.
Further, as shown in FIG. 3A, the thick gate oxide film 111 is removed only in the low withstand voltage region. When the thick gate oxide film 111 is removed, the divot 110 in the low withstand voltage region is further enlarged. In FIG. 3A, the enlarged divot is shown by a reference 110a. Subsequently, as shown in FIG. 3B, a thin gate oxide film 112 for the low withstand voltage MOS transistor is formed.
Successively, as shown in FIG. 3C, a gate electrode is formed over the thick gate oxide film and the thin gate oxide film. Further, by way of steps such as source-drain ion implantation for forming a MOS transistor, a high withstand voltage MOS transistor and a low withstand voltage MOS transistor are formed in the high withstand voltage region and the low withstand voltage region, respectively.
FIG. 4 is a plan view showing a structure of the thus formed high withstand voltage MOS transistor and FIG. 5 is a cross sectional view showing the structure of the high withstand voltage MOS transistor along a cross section I-I′ in FIG. 4. As shown in FIG. 4, the gate electrode 113 is formed so as to traverse an active region 114, and a device isolation region 115 is formed so as to surround the active region 114. The thermal oxide film 108 and the buried oxide film 109 are formed in the device isolation region 115.